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TFP401, TFP401A TI PanelBus DIGITAL RECEIVER
SLDS120B - MARCH 2000 - REVISED JUNE 2003
D Supports UXGA Resolution D D D D D
(Output Pixel Rates Up to 165 MHz) Digital Visual Interface (DVI) Specification Compliant1 True-Color, 24 Bit/Pixel, 16.7M Colors at 1 or 2-Pixels Per Clock Laser Trimmed Internal Termination Resistors for Optimum Fixed Impedance Matching Skew Tolerant Up to One Pixel Clock Cycle 4x Over-Sampling
D Reduced Power Consumption - 1.8 V Core D D D D
Operation With 3.3 V I/Os and Supplies2 Reduced Ground Bounce Using Time Staggered Pixel Outputs Lowest Noise and Best Power Dissipation Using TI PowerPAD Packaging Advanced Technology Using TI 0.18-m EPIC-5 CMOS Process TFP401A Incorporates HSYNC Jitter Immunity3
description
The Texas Instruments TFP401 and TFP401A are TI PanelBus flat panel display products, part of a comprehensive family of end-to-end DVI 1.0 compliant solutions. Targeted primarily at desktop LCD monitors and digital projectors, the TFP401/401A finds applications in any design requiring high-speed digital interface. The TFP401/401A supports display resolutions up to UXGA in 24-bit true color pixel format. The TFP401/401A offers design flexibility to drive one or two pixels per clock, supports TFT or DSTN panels, and provides an option for time staggered pixel outputs for reduced ground bounce. PowerPAD advanced packaging technology results in best of class power dissipation, footprint, and ultra-low ground inductance. The TFP401/401A combines PanelBus circuit innovation with TI's advanced 0.18-m EPIC-5 CMOS process technology, along with TI PowerPAD package technology to achieve a reliable, low-powered, low noise, high-speed digital interface solution.
AVAILABLE OPTIONS PACKAGED DEVICE TA 100-TQFP (PZP) TFP401PZP 0C to 70C TFP401APZP
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1. 2. 3.
The Digital Visual Interface Specification, DVI, is an industry standard developed by the Digital Display Working Group (DDWG) for high-speed digital connection to digital displays The TFP401 and TFP401A are compliant to the DVI Specification Rev. 1.0. The TFP401/401A has an internal voltage regulator that provides the 1.8-V core power supply from the externally supplied 3.3-V supplies. The TFP401A incorporates additional circuitry to create a stable HSYNC from DVI transmitters that introduce undesirable jitter on the transmitted HSYNC signal.
PanelBus, PowerPAD and EPIC-5 are trademarks of Texas Instruments. I2C is a licensed bus protocol from Phillips Semiconductor, Inc.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2000-2003, Texas Instruments Incorporated
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TFP401, TFP401A TI PanelBus DIGITAL RECEIVER
SLDS120B - MARCH 2000 - REVISED JUNE 2003
100-PIN PACKAGE (TOP VIEW)
OGND QO23 OVDD AGND Rx2+ Rx2- AVDD AGND AVDD Rx1+ Rx1- AGND AVDD AGND Rx0+ Rx0- AGND RxC+ RxC- AVDD EXT_RES PVDD PGND RSVD OCK_INV
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
QO22 QO21 QO20 QO19 QO18 QO17 QO16 GND DVDD QO15 QO14 QO13 QO12 QO11 QO10 QO9 QO8 OGND OVDD QO7 QO6 QO5 QO4 QO3 QO2
99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
QO1 QO0 HSYNC VSYNC DE OGND ODCK OVDD CTL3 CTL2 CTL1 GND DVDD QE23 QE22 QE21 QE20 QE19 QE18 QE17 QE16 OVDD OGND QE15 QE14
2
DFO PD ST PIXS GND DVDD STAG SCDT PDO QE0 QE1 QE2 QE3 QE4 QE5 QE6 QE7 OVDD OGND QE8 QE9 QE10 QE11 QE12 QE13
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functional block diagram
3.3 V 3.3 V 1.8 V Regulator Internal 50- Termination RED(0-7) Rx2+ Rx2Rx1+ Rx1Rx0+ Rx0+ _ Channel 2 Latch Channel 1 Latch Channel 0 Latch CH2(0-9) CTL3 CTL2 Data Recovery CH1(0-9) TMDS and Decoder Synchronization CH0(0-9) GRN(0-7) CTL1 BLU(0-7) VSYNC HSYNC Panel Interface 3.3 V
QE(0-23) QO(0-23) ODCK DE SCDT CTL3 CTL2 CTL1 VSYNC HSYNC
+ _
+ _
RxC+ RxC-
+ _
PLL
Terminal Functions
TERMINAL NAME AGND AVDD CTL[3:1] DE NO. 79,83,87, 89,92 82,84,88, 95 42,41,40 46 I/O GND VDD DO DO DESCRIPTION Analog Ground - Ground reference and current return for analog circuitry. Analog VDD - Power supply for analog circuitry. Nominally 3.3 V General-purpose control signals - Used for user defined control. CTL1 is not powered-down via PDO. Output data enable - Used to indicate time of active video display versus non-active display or blank time. During blank, only HSYNC, VSYNC, and CTL1-3 are transmitted. During times of active display, or non-blank, only pixel data, QE[23:0] and QO[23:0], is transmitted. High : Active display time Low: Blank time DFO 1 DI Output clock data format - Controls the output clock (ODCK) format for either TFT or DSTN panel support. For TFT support ODCK clock runs continuously. For DSTN support ODCK only clocks when DE is high, otherwise ODCK is held low when DE is low. High : DSTN support/ODCK held low when DE = low Low: TFT support/ODCK runs continuously. DGND DVDD EXT_RES HSYNC RSVD OVDD ODCK 5,39,68 6,38,67 96 48 99 18,29,43, 57,78 44 GND VDD AI DO DI VDD DO Digital ground - Ground reference and current return for digital core Digital VDD - Power supply for digital core. Nominally 3.3 V Internal impedance matching - The TFP401/40A is internally optimized for impedance matching at 50 . An external resistor tied to this pin will have no effect on device performance. Horizontal sync output Reserved. Must be tied high for normal operation. Output driver VDD - Power supply for output drivers. Nominally 3.3 V Output data clock - Pixel clock. All pixel outputs QE[23:0] and QO[23:0] (if in 2-pixel/clock mode) along with DE, HSYNC, VSYNC and CTL[3:1] are synchronized to this clock.
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Terminal Functions (continued)
TERMINAL NAME OGND OCK_INV NO. 19,28,45, 58,76 100 I/O GND DI DESCRIPTION Output driver ground - Ground reference and current return for digital output drivers ODCK Polarity - Selects ODCK edge on which pixel data (QE[23:0] and QO[23:0]) and control signals (HSYNC, VSYNC, DE, CTL1-3 ) are latched Normal Mode: High : Latches output data on rising ODCK edge Low : Latches output data on falling ODCK edge PD 2 DI Power down - An active low signal that controls the TFP401/401A power-down state. During power down all output buffers are switched to a high impedance state. All analog circuits are powered down and all inputs are disabled, except for PD. If PD is left unconnected an internal pullup will default the TFP401/401A to normal operation. High : Normal operation Low: Power down PDO 9 DI Output drive power down - An active low signal that controls the power-down state of the output drivers. During output drive power down, the output drivers (except SCDT and CTL1) are driven to a high impedance state. When PDO is left unconnected, an internal pullup defaults the TFP401/401A to normal operation. High : Normal operation/output drivers on Low: Output drive power down. PGND PIXS 4 98 GND DI PLL GND - Ground reference and current return for internal PLL Pixel select - Selects between one or two pixels per clock output modes. During the 2-pixel/clock mode, both even pixels, QE[23:0], and odd pixels, QO[23:0], are output in tandem on a given clock cycle. During 1-pixel/clock, even and odd pixels are output sequentially, one at a time, with the even pixel first, on the even pixel bus, QE[23:0]. (The first pixel per line is pixel-0, the even pixel. The second pixel per line is pixel-1, the odd pixel.) High : 2-pixel/clock Low: 1-pixel/clock PVDD QE[8:15] 97 20-27 VDD DO PLL VDD - Power supply for internal PLL Even green pixel output - Output for even and odd green pixels when in 1-pixel/clock mode. Output for even only green pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QE8/pin 20 MSB: QE15/pin 27 QE[16:23] 30-37 DO Even red pixel output - Output for even and odd red pixels when in 1-pixel/clock mode. Output for even only red pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QE16/pin 30 MSB: QE23/pin 37 QO[0:7] 49-56 DO Odd blue pixel output - Output for odd only blue pixel when in 2-pixel/clock mode. Not used, and held low, when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QO0/pin 49 MSB: QO7/pin 56 QO[8:15] 59-66 DO Odd green pixel output - Output for odd only green pixel when in 2-pixel/clock mode. Not used, and held low, when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QO8/pin 59 MSB: QO15/pin 66 QO[16:23] 69-75,77 DO Odd red pixel output - Output for odd only red pixel when in 2-pixel/clock mode. Not used, and held low, when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QO16/pin 69 MSB: QO23/pin 77 QE[0:7] 10-17 DO Even blue pixel output - Output for even and odd blue pixels when in 1-pixel/clock mode. Output for even only blue pixel when in 2-pixel per clock mode. Output data is synchronized to the output data clock, ODCK. LSB: QE0/pin 10 MSB: QE7/pin 17
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Terminal Functions (continued)
TERMINAL NAME RxC+ RxC- Rx0+ Rx0- Rx1+ Rx1- Rx2+ Rx2- SCDT NO. 93 94 90 91 85 86 80 81 8 I/O AI AI AI AI AI AI AI AI DO DESCRIPTION Clock positive receiver input - Positive side of reference clock. TMDS low voltage signal differential input pair Clock negative receiver input - Negative side of reference clock. TMDS low voltage signal differential input pair. Channel-0 positive receiver input - Positive side of channel-0. TMDS low voltage signal differential input pair. Channel-0 receives blue pixel data in active display and HSYNC, VSYNC control signals in blank. Channel-0 negative receiver input - Negative side of channel-0. TMDS low voltage signal differential input pair. Channel-1 positive receiver input - Positive side of channel-1 TMDS low voltage signal differential input pair. Channel-1 receives green pixel data in active display and CTL1 control signals in blank. Channel-1 negative receiver input - Negative side of channel-1 TMDS low voltage signal differential input pair Channel-2 positive receiver input - Positive side of channel-2 TMDS low voltage signal differential input pair. Channel-2 receives red pixel data in active display and CTL2, CTL3 control signals in blank. Channel-2 negative receiver input - Negative side of channel-2 TMDS low voltage signal differential input pair. Sync detect - Output to signal when the link is active or inactive. The link is considered to be active when DE is actively switching. The TFP401/401A monitors the state DE to determine link activity. SCDT can be tied externally to PDO to power down the output drivers when the link is inactive. High: Active link Low: Inactive link ST 3 DI Output drive strength select - Selects output drive strength for high or low current drive. (See dc specifications for IOH and IOL vs ST state.) High : High drive strength Low : Low drive strength Staggered pixel select - An active low signal used in the 2-pixel/clock pixel mode (PIXS = high). Time staggers the even and odd pixel outputs to reduce ground bounce. Normal operation outputs the odd and even pixels simultaneously. High : Normal simultaneous even/odd pixel output Low: Time staggered even/odd pixel output VSYNC 47 DO Vertical sync output
STAG
7
DI
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, DVDD, AVDD, OVDD, PVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Input voltage range, logic/analog signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Operating ambient temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Case temperature for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Package power dissipation/PowerPAD: Soldered (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 W Not soldered (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 W ESD Protection, all pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 KV Human Body Model JEDEC latchup (EIA/JESD78) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Specified with PowerPAD bond pad on the backside of the package soldered to a 2 oz. Cu plate PCB thermal plane. Specified at maximum allowed operating temperature, 70C. 2. PowerPAD bond pad on the backside of the package is not soldered to a thermal plane. Specified at maximum allowed operating temperature, 70C.
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recommended operating conditions
MIN Supply voltage, VDD (DVDD, AVDD, PVDD, OVDD) Pixel time, tpix Single ended analog input termination resistance, Rt 3 6.06 45 50 TYP 3.3 MAX 3.6 40 55 UNIT V ns
Operating free-air temperature, TA 0 25 70 C tpix is the pixel time defined as the period of the RxC clock input. The period of the output clock, ODCK is equal to tpix when in 1-pixel/clock mode and 2tpix when in 2-pixel/clock mode.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
dc digital I/O specifications
PARAMETER VIH VIL IOH IOL High level digital input voltage Low level digital input voltage High level output drive current Low level output drive current ST = High, ST = Low, ST = High, ST = Low, VOH = 2.4 V VOH = 2.4 V VOL = 0.8 V VOL = 0.8 V TEST CONDITIONS MIN 2 0 5 3 10 5 -1 10 6 13 7 TYP MAX DVDD 0.8 14 9 19 11 1 mA A mA UNIT V V
IOZ Hi-Z output leakage current PD = Low or PDO = Low Digital inputs are labeled DI in I/O column of Terminal Functions Table. Digital outputs are labeled DO in I/O column of Terminal Functions Table.
dc specifications
PARAMETER VID VIC VI(OC) IDD(2PIX) IPD IPDO NOTES: 3. 4. 5. Analog input differential voltage (see Note 3) Analog input common mode voltage (see Note 3) Open circuit analog input voltage Normal 2-pix/clock power supply current (see Note 4) Power down current (see Note 5) Output drive power down current (see Note 5) ODCK = 82.5 MHz 2-pix/clock PD = Low PDO = Low 35 TEST CONDITIONS MIN 75 AVDD-300 AVDD-10 TYP MAX 1200 AVDD-37 AVDD+10 370 10 UNIT mv mv mv mA mA mA
Specified as dc characteristic with no overshoot or undershoot. Alternating 2-pixel black/2-pixel white pattern. ST = high, STAG = high, QE[23:0] and QO[23:0] CL = 10 pF. Analog inputs are open circuit (transmitter is disconnected from TFP401/401A).
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electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued)
ac specifications
PARAMETER VID(2) tps tccs tijit tf1 tr1 tr2 tf2 Differential input sensitivity Analog input intra-pair (+ to -) differential skew (see Note 6) Analog Input inter-pair or channel-tochannel skew (see Note 6) Worse case differential input clock jitter tolerance (see Note 6) Fall time of data and control signals#, || Rise time of data and control signals#, || Rise time of ODCK clock# Fall time of ODCK clock# ST = Low, ST = High, ST = Low, ST = High, ST = Low, ST = High, ST = Low, ST = High, CL=5 pF CL=10 pF CL=5 pF CL=10 pF CL=5 pF CL=10 pF CL=5 pF CL=10 pF 1.8 3.8 0.7 0.6 2.5 2.9 2.1 4 1.5 0.5 2.4 2.1 25 12.5 165 82.5 MHz ns ns ns ns 50 2.4 1.9 2.4 1.9 2.4 1.9 2.4 1.9 TEST CONDITIONS MIN 150 TYP MAX 1560 0.4 1 UNIT mVp-p tbit tpix ps ns ns ns ns
1 pixel/clock, PIXS = low, OCK_INV = low tsu1 Setup time, data and control signal to falling edge of ODCK 2 pixel/clock, PIXS = high, STAG/ = high, OCK_INV = low 2 pixel and STAG, PIXS = high, STAG/ = low, OCK_INV = low 1 pixel/clock, PIXS = low, OCK_INV = low th1 Hold time, data and control signal to falling edge of ODCK 2 pixel and STAG, PIXS = high, STAG/ = low, OCK_INV = low 2 pixel/clock, PIXS = high, STAG/ = high, OCK_INV = low 1 pixel/clock, PIXS = low, OCK_INV = high tsu2 Setup time, data and control signal to rising edge of ODCK 2 pixel/clock, PIXS = high, STAG/ = high, OCK_INV = high 2 pixel and STAG, PIXS = high, STAG/ = low, OCK_INV = high 1 pixel/clock, PIXS = low, OCK_INV = high th2 Hold time, data and control signal to rising edge of ODCK 2 pixel and STAG, PIXS = high, STAG/ = low, OCK_INV = high 2 pixel/clock, PIXS = high, STAG/ = high, OCK_INV = high PIX = Low (1-PIX/CLK) fODCK ODCK frequency PIX = High (2-PIX/CLK)
ODCK duty-cycle 45% 60% 75% Specified as ac parameter to include sensitivity to overshoot, undershoot and reflection. tbit is 1/10 the pixel time, tpix tpix is the pixel time defined as the period of the RxC input clock. The period of ODCK is equal to tpix in 1-pixel/clock mode or 2tpix when in 2-pixel/clock mode. Measured differentially at 50% crossing using ODCK output clock as trigger. # Rise and fall times measured as time between 20% and 80% of signal amplitude. || Data and control signals are : QE[23:0], QO[23:0], DE, HSYNC, VSYNC and CTL[3:1] kLink active or inactive is determined by amount of time detected between DE transitions. SCDT indicates link activity. NOTE 6: By characterization
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electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued)
ac specifications
PARAMETER tpd(PDL) tpd(PDOL) tt(HSC) tt(FSC) td(st) Propagation delay time from PD low to Hi-Z outputs Propagation delay time from PDO low to Hi-Z outputs Transition time between DE transition to SCDT lowk Transition time between DE transition to SCDT highk Delay time, ODCK latching edge to QE[23:0] data output STAG = Low Pixs = High 1e6 1600 0.25 TEST CONDITIONS MIN TYP MAX 9 9 UNIT ns ns tpix tpix tpix
8
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PARAMETER MEASUREMENT INFORMATION
tr1 QE(0-23), QO(0-23), DE CTK(1-3), HSYNC, VSYNC 80% 20% tf1 80% 20%
Figure 1. Rise and Fall TIme of Data and Control Signals
tr2 ODCK 80% 20%
tf2 80% 20%
Figure 2. Rise and Fall Time of ODCK
fODCK ODCK
Figure 3. ODCK Frequency
t(su1) VOH VOL VOH VOL VOH VOL
t(su2) t(h1) t(h2) VOH VOL VOH VOL VOH VOL
ODCK
QE(0-23), QO(0-23), DE CTL(1-3), HSYNC, VSYNC
OCK_INV
Figure 4. Data Setup and Hold Time to Rising and Falling Edge of ODCK
ODCK
VOH td(st) tps Tx+ 50% Tx-
QE(O-23)
50%
Figure 5. ODCK High to QE[23:0] Staggered Data Output
Figure 6. Analog Input Intra-Pair Differential Skew
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PARAMETER MEASUREMENT INFORMATION
PD
VIL tpd(PDL)
PDO
VIL tpd(PDOL)
QE(0-23), QO(0-23), ODCK, DE, CTL(1-3), HSYNC, VSYNC, SCDT
QE(0-23), QO(0-23), ODCK, DE, CTL(2-3), HSYNC, VSYNC
Figure 7. Delay From PD Low to Hi-Z Outputs
Figure 8. Delay From PDO Low to Hi-Z Outputs
PD
VIH twL(PDL_MIN) tp(PDH-V) PD VIL
DFO, ST, PIXS, STAG, Rx(0-2)+, Rx(0-2)-, OCK_INV
Figure 9. Delay From PD Low to High Before Inputs are Active
Figure 10. Minimum Time PD Low
TX2
50%
TX1 tccs TX0 50%
Figure 11. Analog Input Channel-to-Channel Skew
tt(HSC) DE
tt(FSC)
SCDT
Figure 12. Time Between DE Transitions to SCDT Low and SCDT High
tDEL
tDEH
DE
Figure 13. Minimum DE Low and Maximum DE High
10
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detailed description
fundamental operation The TFP401/401A is a digital visual interface (DVI) compliant TMDS digital receiver that is used in digital flat panel display systems to receive and decode TMDS encoded RGB pixel data streams. In a digital display system a host, usually a PC or workstation, contains a TMDS compatible transmitter that receives 24 bit pixel data along with appropriate control signals and encodes them into a high-speed low-voltage differential serial bit stream fit for transmission over a twisted-pair cable to a display device. The display device, usually a flat-panel monitor, will require a TMDS compatible receiver like the TI TFP401/401A to decode the serial bit stream back to the same 24 bit pixel data and control signals that originated at the host. This decoded data can then be applied directly to the flat panel drive circuitry to produce an image on the display. Since the host and display can be separated by distances up to 5 meters or more, serial transmission of the pixel data is preferred. To support modern display resolutions up to SXGA a high bandwidth receiver with good jitter and skew tolerance is required. TMDS pixel data and control signal encoding TMDS stands for transition minimized differential signaling. Only one of two possible TMDS characters for a given pixel will be transmitted at a given time. The transmitter keeps a running count of the number of ones and zeros previously sent and transmits the character that will minimize the number of transitions and approximate a dc balance of the transmission line. Three TMDS channels are used to receive RGB pixel data during active display time, DE = high. The same three channels also receive control signals, HSYNC, VSYNC, and user defined control signals CTL[3:1]. These control signals are received during inactive display or blanking-time. Blanking-time is when DE = low. The following table maps the received input data to appropriate TMDS input channel in a DVI compliant system.
RECEIVED PIXEL DATA ACTIVE DISPLAY DE = HIGH Red[7:0] Green[7:0] Blue[7:0] RECEIVED CONTROL DATA BLANKING DE = LOW CTL[3:2] CTL[1: 0] (see Note 6) HSYNC, VSYNC INPUT CHANNEL Channel - 2 (Rx2 ) Channel - 1 (Rx1 ) Channel - 0 (Rx0 ) INPUT CHANNEL Channel - 2 (Rx2 ) Channel - 1 (Rx1 ) Channel - 0 (Rx0 ) OUTPUT PINS (VALID FOR DE = HIGH) QE[23:16] QO[23:16] QE[15:8] QO[15:8] QE[7:0] QO[7:0] OUTPUT PINS (VALID FOR DE = LOW) CTL[3:2] CTL1 HSYNC, VSYNC
NOTE 7: Some TMDS transmitters transmit a CTL0 signal. The TFP401/401A decodes and transfers CTL[3:1] and ignores CTL0 characters. CTL0 is not available as a TFP401/401A output.
The TFP401/401A discriminates between valid pixel TMDS characters and control TMDS characters to determine the state of active display versus blanking, i.e., state of DE.
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detailed description (continued)
TFP401/401A clocking and data synchronization The TFP401/401A receives a clock reference from the DVI transmitter that has a period equal to the pixel time, Tpix. The frequency of this clock is also referred to as the pixel rate. Since the TMDS encoded data on Rx[2:0] contains 10 bits per 8 bit pixel it follows that the Rx[2:0] serial bit rate is 10 times the pixel rate. For example, the required pixel rate to support an UXGA resolution with 60 Hz refresh rate is 165 MHz. The TMDS serial bit rate is 10x the pixel rate or 1.65 Gb/s. Due to the transmission of this high-speed digital bit stream, on three separate channels (or twisted-pair wires) of long distances (3-5 meters), phase synchronization between the data steams and the input reference clock is not guaranteed. In addition, skew between the three data channels is common. The TFP401/401A uses a 4x oversampling scheme of the input data streams to achieve reliable synchronization with up to 1-Tpix channel-to-channel skew tolerance. Accumulated jitter on the clock and data lines due to reflections and external noise sources is also typical of high speed serial data transmission, hence the TFP401/401A's design for high jitter tolerance. The input clock to the TFP401/401A is conditioned by a phase-locked-loop (PLL) to remove high frequency jitter from the clock. The PLL provides four 10x clock outputs of different phase to locate and sync the TMDS data streams (4x oversampling). During active display the pixel data is encoded to be transition minimized, whereas in blank, the control data is encoded to be transition maximized. A DVI compliant transmitter is required to transmit in blank for a minimum period of time, 128-Tpix, to ensure sufficient time for data synchronization when the receiver sees a transition maximized code. Synchronization during blank, when the data is transition maximized, ensures reliable data bit boundary detection. Phase synchronization to the data streams is unique for each of the three input channels and is maintained as long as the link remains active. TFP401/401A TMDS input levels and input impedance matching The TMDS inputs to the TFP401/401A receiver have a fixed single-ended termination to AVDD The TFP401/401A is internally optimized using a laser trim process to precisely fix the impedance at 50 . The device will function normally with or without a resistor on the EXT_RES pin, so it remains drop-in compatible with current sockets. The fixed impedance eliminates the need for an external resistor while providing optimum impedance matching to standard 50- DVI cables. Figure 14 shows a conceptual schematic of a DVI transmitter and TFP401/401A receiver connection. A transmitter drives the twisted pair cable via a current source, usually achieved with an open drain type output driver. The internal resistor, which is matched to the cable impedance, at the TFP401/401A input provides a pullup to AVDD . Naturally, when the transmitter is disconnected and the TFP401/401A DVI inputs are left unconnected, the TFP401/401A receiver inputs pullup to AVDD. The single ended differential signal and full differential signal is shown in Figure 15. The TFP401/401A is designed to respond to differential signal swings ranging from 150 mV to 1.56 V with common mode voltages ranging from (AVDD-300 mV) to (AVDD-37 mV).
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TFP401, TFP401A TI PanelBus DIGITAL RECEIVER
SLDS120B - MARCH 2000 - REVISED JUNE 2003
TFP401/401A TMDS input levels and input impedance matching (continued)
DVI Transmitter TI TFP401/401A Receiver AVDD
DVI Compliant Cable Internal Termination at 50 DATA DATA + _ Current Source
Figure 14. TMDS Differential Input and Transmitter Connection
VIDIFF + 1/2 VIDIFF 1/2 VIDIFF AVCC AVCC - 1/2 VIDIFF a ) Single-Ended Input Signal - 1/2 VIDIFF b) Differential Input Signal
Figure 15. TMDS Inputs TFP401A incorporates HSYNC jitter immunity Several DVI transmitters available in the market introduce jitter on the transmitted HSYNC and VSYNC signals during the TMDS encryption process. The HSYNC signal can shift by one pixel position (one clock) from nominal in either direction, resulting in up to two cycles of HSYNC shift. This jitter carries through to the DVI receiver, and if the position of HSYNC shifts continuously, the receiver can lose track of the input timing and pixel noise will occur on the display. For this reason, a DVI compliant receiver with HSYNC jitter immunity should be used in all displays that could be connected to host PCs with transmitters that have this HSYNC jitter problem. The TFP401A integrates HSYNC regeneration circuitry that provides a seamless interface to these noncompliant transmitters. The position of the data enable (DE) signal is always fixed in relation to data, irrespective of the location of HSYNC. The TFP401A receiver uses the DE and clock signals recreate stable vertical and horizontal sync signals. The circuit filters the HSYNC output of the receiver, and HSYNC is shifted to the nearest eighth bit boundary, producing a stable output with respect to data, as shown in Figure 16. This will ensure accurate data synchronization at the input of the display timing controller.
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TFP401, TFP401A TI PanelBus DIGITAL RECEIVER
SLDS120B - MARCH 2000 - REVISED JUNE 2003
TFP401A incorporates HSYNC jitter immunity (continued) This HSYNC regeneration circuit is transparent to the monitor and need not be removed even if the transmitted HSYNC is stable. For example, the PanelBus line of DVI 1.0 compliant transmitters, such as the TFP6422 and TFP420, do not have the HSYNC jitter problem. The TFP401A will operate correctly with either compliant or noncompliant transmitters. In contrast, the TFP401 is ideal for customers who have control over the transmit portion of the design such as bundled system manufacturers and for internal monitor use (the DVI connection between monitor and panel modules).
ODCK HSYNC Shift by 1 Clock HSYNC IN
DE
HSYNC OUT
Figure 16. HSYNC Regeneration Timing Diagram TFP401/401A modes of operation The TFP401/401A provides systems design flexibility and value by providing the system designer with configurable options or modes of operation to support varying system architectures. The following table outlines the various panel modes that can be supported along with appropriate external control pin settings.
PANEL TFT or 16-bit DSTN TFT or 16-bit DSTN TFT TFT 24-bit DSTN NONE 24-bit DSTN 24-bit DSTN PIXEL RATE 1 pix/clock 1 pix/clock 2 pix/clock 2 pix/clock 1 pix/clock 1 pix/clock 2 pix/clock 2 pix/clock ODCK LATCH EDGE Falling Rising Falling Rising Falling Rising Falling Rising ODCK Free run Free run Free run Free run Gated low Gated low Gated low Gated low DFO 0 0 0 0 1 1 1 1 PIXS 0 0 1 1 0 0 1 1 OCK_INV 0 1 0 1 0 1 0 1
TFP401/401A output driver configurations The TFP401/401A provides flexibility by offering various output driver features that can be used to optimize power consumption, ground-bounce and power-supply noise. The following sections outline the output driver features and their effects. Output driver power down (PDO = low), Pulling PDO low will place all the output drivers, except CTL1 and SCDT, into a high-impedance state. The SCDT output which indicates link-disabled or link-inactive can be tied directly to the PDO input to disable the output drivers when the link is inactive or when the cable is disconnected. An internal pullup on the PDO pin will default the TFP401/401A to the normal nonpower down output drive mode if left unconnected.
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TFP401/401A output driver configurations (continued) Drive Strength (ST = high for high drive strength, ST=low for low drive strength.) The TFP401/401A allows for selectable output drive strength on the data, control and ODCK outputs. See the dc specifications table for the values of IOH and IOL current drives for a given ST state. The high output strength offers approximately two times the drive as the low output drive strength. Time Staggered Pixel Output. This option works only in conjunction with the 2-pixel/clock mode (PIXS = high). Setting STAG = low will time stagger the even and odd pixel output so as to reduce the amount of instantaneous current surge from the power supply. Depending on the PCB layout and design this can help reduce the amount of system ground bounce and power supply noise. The time stagger is such that in 2-pixel/clock mode the even pixel is delayed from the latching edge of ODCK by 0.25 Tcip. (Tcip is the period of ODCK. The ODCK period is 2Tpix when in 2-pixel/clock mode.) Depending on system constraints of output load, pixel rate, panel input architecture and board cost the TFP401/401A drive strength and staggered pixel options allow flexibility to reduce system power-supply noise, ground bounce and EMI. Power Management. The TFP401/401A offers several system power management features. The output driver power down (PDO = low) is an intermediate mode which offers several uses. During this mode, all output drivers except SCDT and CTL1 are driven to a high impedance state while the rest of the device circuitry remains active The TFP401/401A power down (PD = low) is a complete power down in that it powers down the digital core, the analog circuitry, and output drivers. All output drivers are placed into a Hi-Z state. All inputs are disabled except for the PD input. The TFP401/401A will not respond to any digital or analog inputs until PD is pulled high. Both PDO and PD have internal pullups so if left unconnected they will default the TFP401/401A to normal operating modes. Sync Detect. The TFP401/401A offers an output, SCDT to indicate link activity. The TFP401/401A monitors activity on DE to determine if the link is active. When 1 million (1e6) pixel clock periods pass without a transition on DE, the TFP401/401A considers the link inactive and SCDT is driven low. While SCDT is low, if two DE transitions are detected within 1600 pixel clock periods, the link will be considered active and SCDT is pulled high. SCDT can be used to signal a system power management circuit to initiate a system power down when the link is considered inactive. The SCDT can also be tied directly to the TFP401/401A PDO input to power down the output drivers when the link is inactive. It is not recommended to use the SCDT to drive the PD input since, once in complete power-down, the analog inputs are ignored and the SCDT state will not change. An external system power management circuit to drive PD is preferred.
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TFP401, TFP401A TI PanelBus DIGITAL RECEIVER
SLDS120B - MARCH 2000 - REVISED JUNE 2003
TI PowerPAD 100-TQFP package The TFP401/401A is packaged in TI's thermally enhanced PowerPAD 100TQFP packaging. The PowerPAD package is a 14 mm x 14 mm x 1 mm TQFP outline with 0.5 mm lead-pitch. The PowerPAD package has a specially designed die mount pad that offers improved thermal capability over typical TQFP packages of the same outline. The TI 100-TQFP PowerPAD package offers a back-side solder plane that connects directly to the die mount pad for enhanced thermal conduction. Soldering the back side of the TFP401/401A to the application board is not required thermally as the device power dissipation is well within the package capability when not soldered. Soldering the back side of the device to the PCB ground plane is recommended for electrical considerations. Since the die pad is electrically connected to the chip substrate and hence chip ground, connection of the PowerPAD back side to a PCB ground plane will help to improve EMI, ground bounce, and power supply noise performance. Table 1 outlines the thermal properties of the TI 100-TQFP PowerPAD package. The 100-TQFP nonPowerPAD package is included only for reference. Table 1. TI 100-TQFP (14 x 14 x 1 mm)/0.5 mm Lead Pitch
PARAMETER Theta-JA, Theta-JC, WITHOUT PowerPAD 45C/W 3.11C/W PowerPAD NOT CONNECTED TO PCB THERMAL PLANE 27.3C/W 0.12C/W 2.7 W PowerPAD CONNECTED TO PCB THERMAL PLANE 17.3C/W 0.12C/W 4.3 W
Maximum power dissipation,, 1.6 W Specified with 2 oz. Cu PCB plating. Airflow is at 0 LFM (no airflow) Measured at ambient temperature, TA = 70C.
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device TFP401APZP TFP401PZP
(1)
Status (1) ACTIVE ACTIVE
Package Type HTQFP HTQFP
Package Drawing PZP PZP
Pins Package Eco Plan (2) Qty 100 100 90 90 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
Lead/Ball Finish CU NIPDAU CU NIPDAU
MSL Peak Temp (3) Level-3-260C-168 HR Level-3-260C-168 HR
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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